Computer systems are becoming increasingly pervasive in our society including everything from small handheld electronic devices, such as personal digital data assistants and cellular phones, to application-specific electronic components, such as set-top boxes and other consumer electronics, to full mobile, desktop, and server systems. However, as systems become smaller in size and in price, the need for efficient memory allocation and system management becomes more important.
Server systems have been traditionally characterized by a significant amount of conventional memory and multiple physical processors in the same system (a multiprocessor system), wherein a physical processor refers to a single processor die or single package. The significant amount of memory available to a server system has lead to extremely inefficient allocation of memory space and wasted execution time.
Typically, in a multi-processor system, upon boot every processor arbitrates for wake-up, which may include allocating memory and relocating the processor's base address (SMBase). In the process of initializing each processor, a system management interrupt (SMI) is generated, which is handled with a default SMI handler for each processor. Usually, the processors arbitrate with a race to the flag scheme, wherein the first processor to begin handling the SMI is able to begin initialization. Initialization typically includes allocation of a separate and distinct 4 kB aligned memory space for each processor, which forces one to allocate more memory than needed for system management.
Furthermore, when a system management interrupt (SMI) occurs, whether during boot or regular operation, each processor in a multiprocessor system runs a separate and distinct SMI handler to service/handle the SMI. There are two types of SMIs. The first type is an asynchronous interrupt that may be generated by the system hardware, such as when a battery is low. An asynchronous interrupt may be handled separately by any processor, since knowledge of another processor's save state area is not needed to service the request. The second type of interrupt, a synchronous SMI, that is software generated, should be handled by every processor. Typically, a software generated SMI occurs when the operating system (OS) wants a processor to enter system management mode (SMM). SMM is an environment for executing software routines/handlers that does not interfere with the OS or application programs.
In current multiprocessor systems, each processor enters SMM and then one-by-one executes a distinct SMI handler to check their registers to find out which processor generated the SMI. This requires a separate SMI handler be executed for each processor, which introduces resource contention issues, thus making updates to the SMI handler code difficult.
However, these inefficient methods of initialization and handling are not limited to multiprocessor server systems, but exist in other systems, such as mobile multiprocessor systems. Hyper-Threading Technology (HT) is a technology from Intel.RTM. Corporation of Santa Clara, Calif. that enables execution of threads in parallel using a single physical processor. HT incorporates two logical processors on one physical processor (the same die). A logical processor is an independent processor visible to the operating system (OS), capable of executing code and maintaining a unique architectural state from other processor in a system. HT is achieved by having multiple architectural states that share one set of execution resources.
Therefore, HT enables one to implement a multi(logical)processor system in a mobile platform. As shown above, inefficient memory allocation, processor initialization, and SMI handling exist in traditional multiprocessor systems, such as server systems. Furthermore, as multiprocessor systems begin to infiltrate the mobile realm, where resources such as memory are limited, the need for optimizations of the aforementioned inefficiencies becomes even more important.